Integrated circuits, such as ultra-large scale integrated (ULSI) circuits, can include as many as one billion transistors or more. Most typically, ULSI circuits are formed of Field Effect Transistors (FETs) formed in a Complementary Metal Oxide Semiconductor (CMOS) process. Each MOSFET includes a gate electrode formed over a channel region of the semiconductor substrate, which runs between a drain region and source region.
To increase the device density and operation speed of the integrated circuits, the feature size of transistor within the circuits must be reduced. However, with the continued reduction in device size, sub-micron scale MOS transistors have to overcome many technical challenges. As the MOS transistors become smaller and their channel length decreases, problematic short channel effects (SCEs), such as, source to drain leakage become more pronounced.
One solution to decrease the physical dimension of ULSI circuits is to form recessed or buried gate transistors, which have a gate electrode buried in a substrate recess or trench. Such an architecture allows for greater circuit density due to less topography above the silicon surface, thereby creating less ground rule restrictions, and by allowing junction profiles typically on the silicon plane to form on the vertical side of the gate, e.g., source/drain extensions formed under the spacer.
This type of transistor reduces SCEs by increasing the average separation of source and drain without increasing the channel length. By using a vertical dimension, such a structure can also be used to allow a greater overlap of the source/drain under the gate without bringing the source and drain closer. As such the on-state current is increased while the SCEs are not degraded. However, effectively forming recessed gate transistors has been a difficult task.
To reduce SCEs, junction depths are reduced laterally (and vertically) under the gate. However, the reduction of this overlap region (measured by overlap capacitance, Cov) greatly increases the resistance at that point, thereby reducing the on-state current (Ion) and performance of the device. With conventional surface-gates in advanced devices, achieving good SCEs degrades the Ion due to this lack of overlap.
In light of such problems, alternative structures are required to break this Cov-SCEs compromise. There is also a need for these structures to be readily integratable to constitute such a change in MOSFET architecture.